The invention relates in general to systems for testing integrated circuits (ICs), and in particular to a system for distributing a single test signal output of an IC tester to multiple input terminals of one or more ICs and for determining states of output signals produced at multiple IC output terminals.
As illustrated in FIG. 1, an integrated circuit (IC) manufacturer fabricates an array of ICs 12 on a semiconductor wafer 14 and then cuts the wafer to separate the ICs from one another. The manufacturer may then install the ICs in separate packages using bond wires to link the IC""s input/output (I/O) terminals (conductive pads on the surface of each IC) to package pins providing signal paths to external circuits. Some ICs include xe2x80x9credistributionxe2x80x9d layers covering its I/O terminals. Conductors within the redistribution layers link the IC""s I/O terminals to contact pads formed on the top surface of the redistribution layers. The contact pads are larger than the IC""s I/O terminals and are more evenly distributed so that the IC can be mounted directly on printed circuit boards (PCBs), for example by soldering the pads to correspondingly arranged contact pads on the surfaces of the PCBs. Spring contacts can also be used to link the IC""s redistributed contact pads to a PCB""s contact pads. The spring contacts may be formed either on the IC""s contact pads or on the PCB""s contact pads.
ICs may be tested at the wafer level before they are separated from one another or may be tested after they have separated. Referring to FIG. 2, an IC tester 10 for testing an array of ICs 12 residing on a wafer 14 (or for testing an array of singulated ICs held on a tray) typically includes a set of tester channels, each of which may either transmit a test signal to an IC input pad or monitor an IC output signal produced at an IC output pad to determine whether the IC responds correctly to its input signals. A set of coaxial cables 18 provides signal paths between the tester channels and a cable connector 16 on a probe board 20. A set of probes 22 link pads on the lower surface of probe board 20 to the redistribution or I/O terminal pads on the upper surfaces of ICs 12. Various types of structures can be used to implement probes 22 including, for example, wire bond and lithographic spring contacts, needle probes, and cobra probes. When spring contacts are used to implement probes 22 they may be formed either on pads on the upper surfaces of ICs 12 or on pads on the lower surface of probe board 20.
U.S. Pat. No. 6,064,213, issued May 16, 2000 to Khandros et al., incorporated herein by reference, discloses an example of a card assembly designed to contact spring contacts formed on an IC. U.S. patent application Ser. No. 09/810,871 filed Mar. 16, 2001 (incorporated herein by reference) describes another example of a card assembly employing spring contact probes. U.S. Pat. No. 5,974,662 issued Nov. 2, 1999, issued to Eldridge et al., incorporated herein by reference, descries an example of a probe card assembly in which spring contacts formed on a probe card function as probes. The following documents (incorporated herein by reference) disclose various exemplary methods for manufacturing spring contacts: U.S. Pat. No. 6,333,269 issued Jan. 8, 2002 to Eldridge et al., U.S. Pat. No. 6,255,126 issued Jul. 31, 2001 to Mathieu et al., U.S. patent application Ser. No. 09/710,539 filed Nov. 9, 2000, and U.S. patent application Ser. No. 09/746,716 filed Dec. 22, 2000.
Probe board 20 is typically a multiple layer printed circuit board (PCB) providing signal paths between cable connector 16 and the pads on its lower surface. Traces formed on the various layers of probe board 20 convey signals horizontally while vias convey signals vertically though the layers.
Tester 10 typically provides a separate channel for each pad 26 that is linked to an I/O terminal of an IC to be tested. FIG. 3 illustrates one channel 24 of a typical tester accessing a pad 26 of a wafer 14 via a path 36 through a probe card 20. A test is usually organized into a succession of test cycles of uniform duration, and during each test cycle channel 24 may either provide an input to a pad 26 of an IC 12 formed on wafer 14 or may monitor an IC output signal produced by the IC at pad 26 to determine its state. A data acquisition and control circuit 30, programmed via instructions supplied through a bus 42, controls the action channel 24 is to carry out during each test cycle. When pad 26 is to receive an input signal, circuit 30 sets a tristate control input Z of a tristate driver 32 so that the driver supplies a test signal as input to pad 26. Circuit 30 sets an input signal D to driver 32 during each test cycle so that the test signal is of the correct logic state. The test signal travels to pad 26 through a signal path formed by one of cables 18, the signal path 36 provided by probe card 20, and one of probes 22.
When an IC 12 produces an output signal at pad 26, the output signal passes through probe 22, signal path 36 and cable 18 to become an input signal to a pair of comparators 38 and 39 within channel 24. Comparator 38 asserts a compare high (CH) signal when the voltage of IC output signal is higher than a high logic level threshold voltage produced by a digital-to-analog converter (DAC) 40. Comparator 39 asserts a compare low (CL) signal when the IC output signal voltage is lower than a low logic level threshold voltage produced by another digital-to-analog converter (DAC) 41. Circuit 30 supplies control data DREF as input to DACs 40 and 41 for controlling the voltage levels of the VH and VL reference signals.
For example, when the test signal has 5 volt and 0 volt high and low logic levels, the VH and VL threshold levels might be set to 4.5 and 0.5 volts, respectively, so that an IC output signal over 4.5 volts is treated as a high logic level, an IC output signal under 0.5 volts is treated as a low logic level, and an IC output signal between 0.5 and 4.5 volts is considered neither high nor low logic level. Thus comparators 38 and 39 and DACs 40 and 41 can be thought of as an analog-to-digital converter (ADC) producing a 2-bit thermometer code output {CH, CL} indicating one of three ranges in which the input signal voltage lies.
Data acquisition circuit 30 samples the CH and CL bits at a time during each test cycle when the IC output signal is expected to be at a particular logic level. If the IC output signal is expected to be at its high logic level, then the CH bit should be true and the CL bit should be false when sampled. If the IC output signal is expected to be at is low logic level then CL should be true and CH should be false when sampled. An IC under test is considered to be defective when the sampled CH and CL bits representing the state of any of the IC""s output signals are not of their expected states during any test cycle.
In some testers data acquisition and control circuit 30 stores the CH and CL bit for each test cycle in an acquisition memory so that a host computer can access the data via bus 42 at the end of the test and determine whether the IC is defective. In other testers circuit 30 may compare the sampled CH and CL data produced during each test cycle to their expected values and store cycle numbers in an internal memory referencing the particular test cycles, if any, for which the sampled data fails to match their expected values. The host computer then accesses the stored cycle numbers via bus 42.
While tester channels 24 in some testers include two comparators as illustrated in FIG. 3, tester channels in other testers may include only a single comparator. For example when the low and high logic levels of an IC output signal are 0 and 5 volts, respectively, the comparator may be set to drive its single-bit output signal true when the IC output signal exceeds 2.5 volts. Also in many testers channel do not include their own DACs; centralized DACs provide reference voltages in common to all channels.
One drawback to the test system illustrated in FIGS. 2 and 3 is that it requires one tester channel 24 for every pad 26 on wafer 14. Since a wafer 14 can have a large number of ICs 12, and since each IC may have a large number of such pads 26, tester 10 would require a very large number of channels in order to concurrently access all pads 26 of all ICs 12.
What is needed is a system permitting a tester having a limited number of tester channels to concurrently test ICs having a larger number of input and output pads.
Integrated circuits (ICs) formed on a semiconductor typically include conductive pads on their surfaces for receiving IC input signals and for transmitting IC output signals. The invention relates in general to a system for testing ICs before the wafer is cut to separate them, and in particular to an interconnect system for linking a single IC tester channel to multiple (N) IC input or output pads in a way that allows the tester channel to either concurrently transmit a test signal to all N IC input pads or to concurrently monitor and determine states of output signals produced at all N IC output pads.
An interconnect system in accordance with an exemplary embodiment of the invention may include a probe card providing signal paths between the various channels of an IC tester and probes accessing the input and output pads on the surface of the ICs. When a single tester channel is to be connected to each of N IC pads, the probe card provides a branching signal path for distributing the test signal produced by the tester channel to probes accessing each of the N IC pads. Each branch of the path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on the IC input pad accessed via that branch does not substantially affect the voltage of the test signal passing through any other branch.
When a single tester channel is to transmit a test signal to all N IC pads, but is not to monitor IC output signals produced at any N IC pads, the resistance of the resistors included in all path branches may be of similar size. However when a single tester channel is to monitor IC output signals produced at all N IC pads, each branch includes a uniquely sized scaling resistor so that each of the 2N combinations of logic states of the signals produced at the N IC output pads results in a different tester channel input signal voltage. In such case, the tester channel measures the voltage of its input signal and the logic state of each of the signals produced at each of the N IC output pads is determined from the measured voltage of the input signal.
The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant considers to be the best modes of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawings wherein like reference characters refer to like elements.